Method and device for reducing the signal images at the output of a digital/analogue converter

ABSTRACT

Method and device for reducing the signal images at the output of a digital/analogue converter. In a method for reducing the signal images at the output of a digital/analogue converter, a frequency hopping clock generator provides a digital data signal whose data rate is varied according to a frequency hopping method. The digital data signal is converted into an analogue signal by a digital/analogue converter, the conversion clock being varied according to the frequency hopping method.

REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the priority date of German application DE 10 2004 024 645.9, filed on May 18, 2004, the contents of which are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

The invention relates to a method and a device for reducing the signal images at the output of a digital/analogue converter.

BACKGROUND OF THE INVENTION

A synchronous digital/analogue converter (DAC) may be regarded according to FIG. 1 as a circuit which consists of a converter 1 and a holding component 2. This circuit DAC simultaneously implements the following two operations:

converting a number x(nτ) into an electrical variable, for example voltage v(nτ), current i(nτ) or charge q(nτ). The number x(nτ) is usually represented in a binary code. The quantity τ denotes the sampling period, and n denotes the discrete time.

keeping the electrical variable constant over a time interval which corresponds to the sampling period τ or a fraction thereof. The 0^(th) order holding component 2 is used for this. The electrical variable v(t), i(t) or q(t) is provided in a continuous time form at the output of the holding component 2.

FIG. 2A shows a synchronous digital signal in the time domain, i.e. the number x(nτ) plotted against time t. The digital signal can be represented as a sequence of Dirac functions. The sampling period τ corresponds to the inverse of the clock frequency f_(CLK), i.e. 1/f_(CLK). In the frequency domain (FIG. 3A), the digital signal is formed by an infinite number of repetitions of the signal spectrum around positive and negative multiples of the clock frequency, k·f_(CLK), k=0, ±1, ±2, . . . . As usual, the frequency band at d.c. (k=0) is referred to as the baseband and the other frequency bands are referred to as sidebands or signal “images”.

In mathematical terms, the conversion of a number into an electrical variable is merely a change of variables, which does not cause any change of the signal spectrum. There are discrete time sample values (x(nτ) and v(nτ), i(nτ), q(nτ)) before and after the conversion.

In contrast to this, the holding (holding component 2) transforms the signal from the discrete time domain into the continuous time domain, i.e. it changes the nature of the signal. The signal v(t), i(t) or q(t) exists as a sequence of levels in the time domain (FIG. 2B), whereas it is filtered according to the function sin(πf/f_(CLK))/(πf/f_(CLK)) in the frequency domain, see FIG. 3B. This function is conventionally referred to as the sinc function. This “free” filtering attenuates mainly the signal images of the signal since, apart from the baseband, they take the value zero at all multiples of the clock frequency f_(CLK). The attenuation achieved for the signal images is essentially a function of the ratio between the clock frequency f_(CLK) and the bandwidth f_(B) of the signal, i.e. f_(CLK)/f_(B). Large values of the ratio f_(CLK)/f_(B) cause high attenuation of the signal images which, for a given fixed signal bandwidth f_(B), necessitates high clock rates. Large values of the ratio f_(CLK)/f_(B) also mean an increase in the flatness of the frequency excursion in the baseband.

Since a digital/analogue converter is typically intended to generate the signal without the signal images, a filter 3 is conventionally required so as to attenuate the signal images to a particular required amplitude. The filter is often referred to as an anti-image filter (AIF) post filter, reconstruction filter, smoothing filter etc. The filtered signal v*(t), i*(t) or q*(t) at the output of the filter 3 is represented in the time domain (FIG. 2C) and in the frequency domain (FIG. 3C).

For example, a clock frequency f_(CLK)=13 MHz and a signal bandwidth f_(B)=100 kHz ensures “free” attenuation of 44 dB at the lower edge of the first signal image. At the baseband edge, the flatness of the signal is about 8.45·10⁻⁴ dB. With an additional filter 3, it is possible to achieve higher attenuations and flatnesses.

Primarily two approaches have to date been adopted so as to achieve high attenuation of the signal images. The first option is to increase the ratio f_(CLK)/f_(B) and therefore raise the “free” sinc(f) attenuation. In industrial applications, values of the ratio f_(CLK)/f_(B) of the order of several hundred are customary. A disadvantage is the high power use and the great requirement for chip area entailed by an increase in the clock rate. A second option is to use continuous time smoothing filters 3, the order of which is given by a balance between the intended attenuation at the first signal image, the frequency flatness in the baseband and the implementation technology (tuned or untuned). Again, significant costs are incurred with respect to the power consumption, the chip area and the development of such circuits.

At least theoretically, an alternative to the aforementioned options consists in implementing a higher-order holding function at the output of the digital/analogue converter. Instead of keeping the electrical variable constant over the clock period τ (keeping the electrical variable constant is referred to as zeroth-order holding), the electrical variable is selected so that it takes information about the preceding values into account when determining the current value (this corresponds precisely to the mode of operation of a filter). It can be shown that higher-order holding components 2 produce higher-order sinc^(k)(f) functions with k=2, 3, . . . . This concept, however, is very difficult to implement in practice.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

The present invention provides a method and a device which make it possible to suppress or attenuate the signal images at the output of a digital/analogue converter.

In accordance with an aspect of the present invention, a method for reducing the signal images at the output of a digital/analogue converter comprises providing a digital data signal, the data rate of which is varied according to a frequency sequence of a frequency hopping method, and converting the digital data signal into an analogue signal, the conversion clock being varied according to the frequency sequence.

The frequency hopping method is a known technique, which is commonly used in telecommunications systems. It is characterized by a carrier frequency of the transmitter changing (“hopping”) periodically in the time domain. The frequency changes are given by a frequency sequence f₁, f₂, f₃, . . . . The receiver knows the frequency sequence and is constantly tuned to the current carrier frequency of the transmitter in accordance with the sequence. The frequency hopping method allows low-perturbation signal transmission, since interference in one of the frequency channels impairs the transmission quality only briefly because of the rapid frequency change. The frequency hopping method furthermore guarantees a high degree of data security, since external receivers do not know the frequency sequence and can therefore be tuned to the transmitter only rarely or briefly.

The mode of operation of the method according to the invention consists in distributing or spreading the power of the first signal image over a broader bandwidth because of the periodically changing data rate and clock frequency. The attenuation of the first signal image is therefore increased in comparison with the case without a frequency hopping method (i.e., with a data rate and clock frequency constant over time). The additional attenuation which can be achieved by the method according to the invention is generally dependent on the ratio of the bandwidths which are occupied by the signal images in the case without a frequency hopping method and in the case with a frequency hopping method.

One advantage of the method according to the invention is that the smoothing filter may either be entirely obviated or may have a lower order.

A first configuration of the method according to the invention is characterized in that the data rate of a predetermined digital input data signal is varied according to the frequency hopping method by means of a data rate converter when providing a data signal. Methods for changing the data rate of a signal are known in the technology of digital multirate signal processing, see for example the book “Digital Signal Processing”, J. G. Proakis et al., Prentice Hall, 1996, pages 790-792. The data rate variation is preferably carried out by interpolation and decimation.

Another option is to generate the digital data signal with a varying data rate by means of a signal generator. In this case, it is not necessary to carry out data rate conversion of an incoming external input data signal, since the data rate varying according to the invention is already taken into account in the signal generation.

In this case, an advantageous variant of the method is characterized in that the signal generation is carried out by reading data words from a memory with a reading clock dictated by the frequency sequence and an addressing rule selected as a function of the current reading clock.

In accordance with another aspect of the invention, a device according to the invention for reducing the signal images at the output of a digital/analogue converter comprises a frequency hopping clock generator, which generates a clock signal with a clock frequency varying according to a frequency sequence of a frequency hopping method. The device furthermore contains a means driven by the frequency hopping clock generator for providing a digital data signal with a data rate corresponding to the clock signal, and a digital/analogue converter clocked by the clock signal for converting the digital data signal into an analogue signal.

To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be explained in more detail below with the aid of exemplary embodiments, with reference to the drawings in which:

FIG. 1 shows an outline representation of a digital/analogue converter with a downstream smoothing filter.

FIG. 2A shows a representation of the sampled signal in the time domain.

FIG. 2B shows a representation of the held signal in the time domain.

FIG. 2C shows a representation of the smoothed signal in the time domain.

FIG. 3A shows a representation of the sampled signal in the frequency domain.

FIG. 3B shows a representation of the held signal in the frequency domain.

FIG. 3C shows a representation of the smoothed signal in the frequency domain.

FIG. 4 shows a block diagram of a digital/analogue converter with a downstream smoothing filter according to the prior art.

FIG. 5 shows a block diagram of a digital/analogue converter according to the invention with an optional smoothing filter.

FIG. 6 shows a sine generator for generating an analogue sine signal.

DETAILED DESCRIPTION OF THE INVENTION

One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale.

According to FIG. 4, a digital block 4 is driven by a clock generator 5 which emits a clock signal 6 with a fixed clock frequency f_(CLK). The digital block 4 delivers digital data words (word width N) via a data connection 7 to a digital/analogue converter 8. The data rate is f_(CLK), i.e. it corresponds to the clock frequency of the clock signal.

The clock signal 6 furthermore drives the clock input of the digital/analogue converter 8. The mode of operation of the digital/analogue converter 8 and of the downstream smoothing filter 3 have already been described in relation to FIGS. 1-3C.

FIG. 5 shows an exemplary embodiment of a device according to the invention. Components which are the same or functionally equivalent as in the previous figures are denoted by the same references. The digital block 40 is driven by a frequency hopping clock generator 50, which is likewise connected to the clock input of the digital/analogue converter 8. The clock frequency f_(CLK) is given by a frequency sequence f₁, f₂, f₃, . . . . The digital block 40 allows data rate conversion of the digital signal delivered via the data connection 7, according to the clock signal 6 which is received.

The mode of operation of the device represented in FIG. 5 will be explained below with reference to an example:

For the signal bandwidth f_(B) and the reference clock frequency f_(CLK), the values f_(B)=100 kHz and f_(CLK)==13 MHz will be assumed.

The digital block 40 furthermore makes it possible to generate a data rate of 12.8 MHz and 13.2 MHz. To this end, the frequency hopping clock generator 50 generates the clock frequency f_(CLK)=13 MHz for one third of the time, the clock frequency f_(CLK)=13.2 MHz for another third of the time and the clock frequency f_(CLK)=12.8 MHz for the remaining third of the time. This causes the following:

the baseband signal always remains within the frequency interval [−f_(B), f_(B)], regardless of the clock frequency at which the data are converted by the digital/analogue converter 8.

the power of the first image of the signal lies around 12.8 MHz for ⅓ of the time, around 13 MHz for another ⅓ of the time and around 13.2 MHz for the remaining ⅓ of the time. The power contained in the first signal image is therefore distributed over a broader bandwidth, so that additional attenuation is achieved at each frequency compared with the case without a frequency hopping method (i.e. with a fixed clock frequency f_(CLK)). The power reduction in this simple example is −4.8 dB.

In practice, a larger number of alternative frequencies should be taken into account. In particular, it is possible to provide a pseudo-random frequency sequence, such as code division communications systems, with frequency hopping.

There are various ways in which the digital block 40 may be produced. A first option is for the digital block 40 to be a data rate converter. In this case, the digital block 40 is provided (not shown) with an input data signal which has its data rate varied according to the clock signal 6. For example, the data rate converter may be constructed from a series circuit of an interpolator (which increases the data rate by a particular factor) and a decimation circuit (which decreases the data rate by a particular factor). For example, FIR filters or polyphase filters may be used for the interpolation. The decimation may likewise be carried out by a polyphase filter. Further information can be found on pages 792-803 of the textbook by J. G. Proakis cited in the introduction, which are hereby incorporated into the content of the present document by reference.

Another option is for the digital block 40 to represent a digital generator, see FIG. 6. The signal generator comprises, for example, a memory 9 with a memory chip capacity D of, for example, D=1024 data words with a word width of N bits. Each data word contains a sample value of a sine function, which is sampled with a phase increment of 2π/1024 rad. The memory 9 is thus loaded with a full period of a sine function. It is also possible to load the memory 9 merely with sample values relating to ¼ of the period of the sine function, in which case the symmetry of the sine function with respect to the period quarters is exploited.

Instead of a sine function, of course, it is also possible for the memory 9 to store the sample values of other periodic functions, or even non-periodic functions defined over an infinite definition range.

An address input AD of the memory 9 is driven via an address generator 10. The address generator 10 is connected via a control data connection 11 to a frequency hopping clock generator 50′. The latter differs from the frequency hopping clock generator 50 of FIG. 5 in that it furthermore contains an increment generator. The rest of the circuit structure corresponds to the representation in FIG. 5.

If the data words of the memory 9 are read at a clock frequency f_(CLK)=1 MHz with an address increment INCR=1 (the address increment INCR is communicated from the increment generator to the address generator 10 via the control data line 11, and indicates the difference between two successive address values), then approximately one thousand clock periods are needed in order to read a full sine period from the memory 9. This means that a frequency f_(GEN) of about 1 kHz is generated. The following applies f _(GEN)=1/Df _(CLK) ·INCR.

For a given memory capacity D, the address increment INCR and/or the clock frequency f_(CLK) can be used to synthesize other signal frequencies f_(GEN). For the example of a signal generator with a constant frequency f_(GEN) as described here, the product f_(CLK)·INCR has to be kept constant. For example, the following frequency hopping scheme may be carried out:

If f_(CLK)=1 MHz and INCR=10, a frequency f_(GEN)=10 kHz will be generated, and the first signal images lie at 990 kHz and 1010 kHz.

If INCR=11 and f_(CLK)=10/11 MHz (≈909 kHz) , a frequency f_(GEN)=10 kHz will likewise be generated, but the first signal images now lie at approximately 899 kHz and 919 kHz.

If INCR=9 and f_(CLK)=10/9 MHz (≈1,111 kHz), a frequency f_(GEN)=10 kHz will likewise be generated, although the first signal images now lie at approximately 1101 kHz and 1121 kHz.

If the value pairs (f_(CLK), INCR) are selected from a set of P alternatives, and the frequency hopping sequence f_(CLK)=f₁, f₂, f₃, . . . f_(P) is a pseudo-random sequence, then each signal image of the generated signal will be distributed over P pitches, each pitch having an average power of 1/P.

It is clear that in all practical applications, the number P of different frequencies involved in the frequency hopping method may be substantially more than 3.

Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.” 

1. A method for reducing signal images at an output of a digital/analogue converter comprising: providing a digital data signal, wherein the data rate of the digital signal is varied according to a frequency sequence of a frequency hopping method; and converting the digital data signal into an analogue signal employing a conversion clock being varied according to the frequency sequence.
 2. The method of clail 1, wherein providing the digital data signal comprises varying a data rate of a predetermined digital input data signal according to the frequency sequence by means of a data rate converter.
 3. The method of claim 1, wherein the data rate variation is carried out by interpolation and decimation.
 4. The method of claim 1, wherein varying the data rate of the digital signal is performed by a signal generator.
 5. The method of claim 4, wherein the signal generator performs varying the data rate by reading data words from a memory with a reading clock dictated by the frequency sequence and an addressing rule selected as a function of a current reading clock.
 6. The method of claim 4, wherein the signal generator is a sine function generator.
 7. The method of claim 1, wherein the frequency sequence is a pseudo-random sequence.
 8. A system for reducing signal images at an output of a digital/analogue converter comprising: a frequency hopping clock generator, which generates a clock signal with a clock frequency varying according to a frequency sequence of a frequency hopping method; a digital block driven by the frequency hopping clock generator for providing a digital data signal with a data rate corresponding to the clock signal; and a digital/analogue converter clocked by the clock signal for converting the digital data signal into an analogue signal.
 9. The system of claim 8, wherein the digital block is a digital rate converter, which varies the data rate of a predetermined digital input data signal according to the clock signal.
 10. The system of claim 9, wherein the data rate converter comprises a series circuit having at least an interpolator and a decimator circuit.
 11. The system of claim 8, wherein the digital block is a signal generator.
 12. The system of claim 11, wherein the signal generator comprises a memory from which data words are read with a reading clock dictated by the frequency sequence and an addressing rule selected as a function of the reading clock.
 13. The system of claim 11, wherein the signal generator is a sine function generator.
 14. The system of claim 8, wherein the frequency sequence is a pseudo-random sequence.
 15. A system for reducing signal images at an output of a digital/analogue converter comprising: a clock generator that generates a clock signal; a data rate converter that receives the clock signal and a digital data signal and generates a modified digital data signal according to the generated clock and a predetermined frequency sequence from the digital data signal; and a digital/analogue converter that converts the modified digital data signal into an analogue signal according to the generated clock signal.
 16. The system of claim 15, wherein the data rate converter generates the predetermined frequency sequence according to predetermined and periodic amounts.
 17. The system of claim 16, further comprising a receiver that receives the analogue signal and obtains the data signal by utilizing the predetermined frequency sequence.
 18. A method for reducing signal images at an output of a digital/analogue converter comprising: providing a first data signal; generating a clock signal; selecting a frequency sequence for transmitting and receiving; generating a modified digital data signal with a varying data rate from the first data signal according to the frequency sequence; and converting the modified digital data signal into an analogue signal according to the generated clock signal.
 19. The method of claim 18, wherein selecting the frequency sequence comprises selecting the frequency sequence according to a desired attenuation.
 20. The method of claim 18, wherein selecting the frequency sequence comprises selecting the frequency sequence according to a desired power spread. 